The present invention relates generally to semiconductor devices, and more particularly to the formation of air gap structures in a semiconductor device with a bilayer selective cap.
Semiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. To improve the performance of the circuits, low k dielectric materials, having a dielectric constant of less than silicon dioxide, are used between circuits as inter-layer dielectric (ILD) to reduce capacitance. Interconnect structures made of metal lines are usually formed in and around the ILD material to connect elements of the circuits. Within a typical interconnect structure, metal lines run parallel to the semiconductor substrate. An interconnect structure may consist of multilevel or multilayered schemes, such as, single or dual damascene wiring structures.
Manufacture of a semiconductor device, also called an electronic device or integrated circuit, is normally divided into two major phases. The “front end of the line” (FEOL) is dedicated to the creation of all transistors in the body of the semiconductor devices, and the “back end of the line” (BEOL) creates the metal interconnect structures which connect the transistors to each other, as well as provide power to the devices. Once all active components are created, the BEOL manufacturing begins.
Air gap structures, which may be used in flash memory chips, are known to reduce capacitance in the interconnect back end of the line (BEOL) structures of high performance integrated circuits. Integration processes used in the formation of air gap structures are known in some cases to attack the copper (Cu) conductors, resulting in poor reliability, an increase in resistance, and open conductors.